In recent years, it has been desired that the thicknesses and sizes of electronic apparatuses be reduced and the functions operate at a high speed. Such electronic apparatuses include microcomputers having a memory with a large capacity and a high speed. In order to rapidly spread personal computers and enhance their performance to implement higher speed processing, an increase in the capacity of cache memory has been required.
For a RAM, a DRAM (Dynamic RAM) and a SRAM are generally used. The SRAM is usually used for high speed processing as in the cache memory. For the structure of a memory cell of the SRAM, there have been known a high resistance load type constituted by four transistors and two high resistance elements and a CMOS type constituted by six transistors. In particular, since a CMOS type SRAM has a high reliability because of a very small leakage current during data hold, it is a the mainstream SRAM type.
FIG. 10 is an equivalent circuit diagram showing a memory cell of a conventional CMOS type SRAM. In FIG. 10, a PMOS transistor P1 and an NMOS transistor N1 constitute a first CMOS inverter. Moreover, a PMOS transistor P2 and an NMOS transistor N2 constitute a second CMOS transistor. An input/output terminal is complementarily connected between the first and second CMOS inverters.
More specifically, the MOS transistors P1, P2, N1 and N2 constitute a flip-flop circuit. In FIG. 10, a logical state can be written and read in a storage node NA as an output point of the first CMOS inverter and an input point of the second CMOS inverter and a storage node NB as an output point of the second CMOS inverter and an input point as the first CMOS inverter.
Moreover, NMOS transistors N3 and N4 function as access gates respectively. The NMOS transistor N3 has a gate connected to a word line WL, a source connected to the storage node NA, and a drain connected to a positive phase bit line BL1. Moreover, the NMOS transistor N4 has a gate connected to the word line WL, a source connected to the storage node NB, and a drain connected to a negative phase bit line BLB.
In other words, a storage value held in the storage node NA or NB can be read by selecting the word line WL, the positive phase bit line BL, and the negative phase bit line BLB.
FIG. 11 is a diagram showing an example of the layout structure of the conventional SRAM memory cell illustrated in FIG. 10. As shown in FIG. 11, one SRAM memory cell is formed on an N type well region NW and a P type well region PW which are formed on a semiconductor substrate. The PMOS transistors P1 and P2 shown in the equivalent circuit are formed in the same N well region NW and the NMOS transistors N1 to N4 are formed in the same P well region PW.
In FIG. 11, the PMOS transistor P1 sets P+ diffusion regions FL100 and FL110 formed by implanting a P type impurity to be source and drain regions respectively and sets a gate region between the P+ diffusion regions FL100 and FL110 and a polysilicon wiring layer PL110. Similarly, the PMOS transistor P2 sets P+ diffusion regions FL100 and FL120 formed by implanting a P type impurity to be source and drain regions respectively and sets a gate region between the P+ diffusion regions FL100 and FL120 and a polysilicon wiring layer PL120. In other words, the PMOS transistors P1 and P2 share the P+ diffusion region FL100 as the source region.
In FIG. 11, moreover, the NMOS transistor N1 sets N+ diffusion regions FL200 and FL210 formed by implanting an N type impurity to be source and drain regions respectively and sets a gate region between the N+ diffusion regions FL200 and FL210 and a polysilicon wiring layer PL110. Similarly, the NMOS transistor N2 sets N+ diffusion regions FL200 and FL220 formed by implanting an N type impurity to be source and drain regions respectively and sets a gate region between the N+ diffusion regions FL200 and FL220 and the polysilicon wiring layer PL120. In other words, the NMOS transistors N1 and N2 share the N+ diffusion region FL200 as the source region.
Moreover, the NMOS transistor N3 sets N+ diffusion regions FL230 and FL210 formed by implanting an N type impurity to be source and drain regions respectively and sets a gate region between the N+ diffusion regions FL230 and FL210 and a polysilicon wiring layer PL140. In other words, the NMOS transistors N1 and N3 share the N+ diffusion region FL210 as the source region.
Furthermore, the NMOS transistor N4 sets N+ diffusion regions FL240 and FL220 formed by implanting an N type impurity to be source and drain regions respectively and sets a gate region between the N+ diffusion regions FL240 and FL220 and a polysilicon wiring layer PL130. In other words, the NMOS transistors N2 and N4 share the N+ diffusion region FL220 as the drain region.
In the above-mentioned structure, furthermore, the polysilicon wiring layer PL110 also functions as a wiring for connecting the gate regions of the PMOS transistor P1 and the NMOS transistor N1. Similarly, the polysilicon wiring layer PL120 also functions as a wiring for connecting the gate regions of the PMOS transistor P2 and the NMOS transistor N2.
Moreover, at least one contact (connecting hole) is formed in each of the P+ diffusion regions FL100, FL110 and FL120, the N+ diffusion region FL200, FL210, FL220, FL230 and FL240 and the polysilicon wiring layers PL110, PL120, PL130 and PL140. In order to implement the connecting structure of the equivalent circuit shown in FIG. 10, the contacts are connected to each other through an upper wiring layer such as a metal.
Referring to the upper wiring layer for connecting the contacts, various structure have been proposed. For easy understanding, FIG. 11 simply shows a connection wiring between the contacts in a thick solid line. As shown in FIG. 11, the P+ diffusion region FL110, the N+ diffusion region FL210 and the polysilicon wiring layer PL120 are electrically connected through the upper wiring layer, thereby forming the storage node NA, and the P+ diffusion region FL120, the N+ diffusion region FL220 and the polysilicon wiring layer PL110 are electrically connected through the upper wiring layer, thereby forming the storage node NB.
In FIG. 11, moreover, the P+ diffusion region FL100 is connected to a VDD line to be a power line through the contact and the upper wiring layer, and the N+ diffusion region FL200 is connected to a GND line to be a grounding line through the contact and the upper wiring layer. Moreover, the N+ diffusion regions FL230 and FL240 are electrically connected to the positive phase bit line BL and the negative phase bit line BLB through the contact and the upper wiring layer, respectively. Furthermore, the polysilicon wiring layers PL130 and PL140 are electrically connected to the word line WL through the contact and the upper wiring layer.
FIG. 11 shows the SRAM memory cell according to an example of the layout structure for one bit. Next, explanation will be given about the layout structure of a cell array by providing a plurality of SRAM memory cells. FIG. 12 is a diagram showing an example of the layout structure of a memory cell array constituted by the conventional SRAM memory cell. In particular, FIG. 12 shows a plurality of SRAM memory cells provided in a matrix for three adjacent bits. In FIG. 12, common portions to those in FIG. 11 have the same reference numerals and description thereof will be omitted.
As shown in FIG. 12, the SRAM memory cells shown in FIG. 11 are alternately arranged with a variation in a direction by 180 degrees in a multi-bit structure in which a plurality of SRAM memory cells are provided. For example, a memory cell MC1 is inverted with respect to an X axis on upper side of a memory cell MC0. Similarly, a memory cell MC2 is inverted with respect to the X axis on the lower side of a memory cell MC0. As shown in FIG. 12, moreover, the memory cells MC0 and MC1 are formed by sharing one well region NW1, and the memory cells MC0 and MC2 are formed by sharing one well region PW2.
More specifically, if the boundary of the adjacent memory cells is an N well, the P+ diffusion region forming each of the storage nodes NA and NB is formed in a common N well region. Similarly, if the boundary of the adjacent memory cells is a P well, the N+ diffusion region forming each of the storage nodes NA and NB is formed in a common P well region.
Next, the operation of the conventional SRAM memory cell will be described. In the equivalent circuit of FIG. 10, for example, if the storage node NA is set in an electric potential state having a logical level of “H”, the storage node NB is brought into an electric potential state having a logical level of “L” and is thus stabilized. To the contrary, if the storage node NA is set in the electric potential state having the logical level of “L”, the storage node NB is brought into the electric potential state having the logical level of “H” and is thus stabilized. Thus, the memory cell constituted by the complementary connection of the CMOS inverters has two different stable logical states depending on whether the two storage nodes NA and NB are set in the “H” or “L” state, and holds the logical state as one-bit hold data.
Thus, the semiconductor storage device constituted by the CMOS inverter has a very high stability and has no drawback in noise resistance. However, when a memory cell for one bit is caused to be finer in order to implement a memory cell array having a large capacity in which a large number of memory cells are integrated, there is a problem of a soft error in that the data held in the storage node are inverted due to electrons generated by incident α rays or neutrons from the universe.
In particular, the soft error more readily occurs when the source voltage is decreased. In a recent semiconductor storage device which can enhance low-power driving, therefore, increasing the tolerance, i.e., resistance, to soft error is an important theme.
A mechanism for the data inversion caused by the soft error will be briefly described below. First of all, when the α rays or the neutrons are particularly irradiated toward a well in a semiconductor layer of the semiconductor storage device, a large number of electron and hole pairs are generated in the well. The electron and hole pairs thus generated are collected into a diffusion region in accordance with an electric potential distribution generated by a PN junction between the well and the diffusion region. In the P well region, particularly, the electrons in the generated electron and hole pairs are collected into the N+ diffusion region in the same P well region and drop the electric potential of the N+ diffusion region. In the N well region, moreover, the holes in the generated electron and hole pairs are collected into the P+ diffusion region in the same N well region and drop the electric potential of the P+ diffusion region.
In the case in which the N+ diffusion region collecting the electrons or the P+ diffusion region collecting holes is the storage node and the collected electrons or holes have a critical charge quantity or more in the diffusion region, the data held in the storage node are inverted by the electrons or the holes. More specifically, the contents stored and held in the semiconductor storage device are changed due to the irradiation by the α rays and the neutrons in some cases. For this reason, there is a problem in that an initial storage state cannot be completely complemented.